📖 Chip Multiprocessor Architecture
Friday, July 27, 2018 by dev
Chip Multiprocessor Architecture
By:Kunle Olukotun,Oyekunle Ayinde Olukotun,Lance Stirling Hammond,James Laudon
Published on 2007 by Morgan & Claypool Publishers
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. After a discussion of the basic pros and cons of CMPs when they are compared with conventional uniprocessors, this book examines how CMPs can best be designed to handle two radically different kinds of workloads that are likely to be used with a CMP: highly parallel, throughput-sensitive applications at one end of the spectrum, and less parallel, latency-sensitive applications at the other. Throughput-sensitive applications, such as server workloads that handle many independent transactions at once, require careful balancing of all parts of a CMP that can limit throughput, such as the individual cores, on-chip cache memory, and off-chip memory interfaces. Several studies and example systems, such as the Sun Niagara, that examine the necessary tradeoffs are presented here. In contrast, latency-sensitive applications - many desktop applications fall into this category - require a focus on reducing inter-core communication latency and applying techniques to help programmers divide their programs into multiple threads as easily as possible. This book discusses many techniques that can be used in CMPs to simplify parallel programming, with an emphasis on research directions proposed at Stanford University. To illustrate the advantages possible with a CMP using a couple of solid examples, extra focus is given to thread-level speculation (TLS), a way to automatically break up nominally sequential applications into parallel threads on a CMP, and transactional memory. This model can greatly simplify manual parallel programming by using hardware - instead of conventional software locks - to enforce atomic code execution of blocks of instructions, a technique that makes parallel coding much less error-prone. Book jacket.
This Book was ranked at 21 by Google Books for keyword chip.
Book ID of Chip Multiprocessor Architecture's Books is spZZDwuAgUYC, Book which was written byKunle Olukotun,Oyekunle Ayinde Olukotun,Lance Stirling Hammond,James Laudonhave ETAG "ksvq5G+kpk8"
Book which was published by Morgan & Claypool Publishers since 2007 have ISBNs, ISBN 13 Code is 9781598291223 and ISBN 10 Code is 159829122X
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